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Features
* * * * * * * * * * *
Reference Oscillator up to 15 MHz (Tuned) Oscillator Buffer Output (for AM Up/Down Conversion) Two Programmable 16-bit Dividers Fine-tuning Steps Possible Fast Response Time Due to Integrated Loop Push-pull Stage 3-wire Bus (Enable, Clock and Data; 3V and 5V Microcontrollers Acceptable) Four Programmable Switching Outputs (Open Drain) Three DACs for Software Controlled Tuner Alignment Low-power Consumption High Signal to Noise Ratio (SNR) Integrated Band Gap - Only One Supply Voltage Necessary
1. Description
The ATR4256 is a synthesizer IC for FM receivers and an AM up-conversion system in BiCMOS technology. Together with the AM/FM IC ATR4258 or ATR4255, it comprises a complete AM/FM car radio front-end, which is also recommended for RDS (Radio Data System) applications. It is controlled by a 3-wire bus and also contains switches and Digital to Analog Converters (DACs) for software-controlled alignment of the AM/FM tuner. The ATR4256 is the pin-compatible successor IC of U4256BM-R. Figure 1-1. Block Diagram
SWO1 SWO2 SWO3 SWO4 7 Tuning 13 12 Oscillator Switching outputs DAC3 3-bit V Ref DAC2 3-wire bus interface 4 5 8 9 10
Frequency Synthesizer for Radio Tuning ATR4256
OSCIN OSCOUT
DAC3
MX2LO
15
OSC buffer
CLK DATA EN
17 16 18
DAC2
DAC1
3
DAC1
Rdivider
DAC AM/FM
VRef
FMOSCIN
19
FMpreamp
Ndivider
Phase detector
Current sources
1
PDO
Band gap 20 GNDAN V5 14 11 GND VS 6
2
PD
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2. Pin Configuration
Figure 2-1. Pinning SSO20
FMOSCIN OSCOUT 12 SWO3 9 GNDAN MX2LO OSCIN
DATA
CLK
20
19
18
17
16
15
ATR4256
14
13
Table 2-1.
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Pin Description
Symbol PDO PD DAC1 DAC2 DAC3 VS SWO1 SWO2 SWO3 SWO4 GND OSCOUT OSCIN V5 MX2LO DATA CLK EN FMOSCIN GNDAN Function Phase detector output Pulsed current output Digital-to-analog converter 1 Digital-to-analog converter 2 Digital-to-analog converter 3 Supply voltage, analog part Switching output 1 Switching output 2 Switching output 3 Switching output 4 Ground, digital part Reference oscillator output Reference oscillator input Capacitor band gap Oscillator buffer output Data input Clock Enable FM-oscillator input Ground, analog part
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SWO2
DAC1
DAC3
SWO4 10
1
4
5
2
3
6
DAC2
SWO1
PDO
PD
VS
7
8
11 GND
EN
V5
ATR4256
3. Functional Description
For a tuned FM-broadcast receiver, the following parts are needed: * Voltage-controlled Oscillator (VCO) * Antenna Amplifier Tuned Circuit * RF Amplifier Tuned Circuit Typical modern receivers with electronic tuning are tuned to the desired FM frequency by the frequency synthesizer IC ATR4256. The special design allows the user to build software-controlled tuner alignment systems. Two programmable DACs (Digital-to-Analog Converter) support the computer-controlled alignment. The output of the PLL is a tuning voltage which is connected to the VCO of the receiver IC. The output of the VCO is equal to the desired station frequency plus the IF (10.7 MHz). The RF and the oscillator signal (VCO) are both input to the mixer that translates the desired FM-channel signal to the fixed IF signal. For FM, the double-conversion system of the receiver requires exactly 10.7 MHz for the first IF frequency, which determines the center frequency of the software-controlled integrated second IF filter. If this oscillator tuning feature is not used, the internal capacitors have to be switched off and the oscillator has to be operated with high-quality external capacitors to ensure that the operational frequency is exactly 10.250 MHz. When dimensioning the oscillator circuit, it is important that the additional capacitors enable the oscillator to operate through its complete tracking range. The oscillating ability depends very strongly on the used crystal oscillator. Initializing the oscillator should be established without switching any additional capacitors to guarantee that the oscillator starts to operate properly. Due to the lower quality of the integrated capacitors compared to discrete capacitors, the amount of the switched integrated capacitors should always be minimized. (If necessary reduce tracking range or use a different crystal oscillator.) The ATR4256 has a very fast response time of maximum 800 s (at 2 mA, fStep = 50 kHz, measured on the MPX signal). It has a high signal to noise ratio. Only one supply voltage is necessary, due to an integrated band gap.
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4. Input/Output Interface Circuits
4.1 PDO (Pin 1)
PDO is the buffer amplifier output of the PLL. The bipolar output stage is a rail-to-rail amplifier.
4.2
PD (Pin 2)
PD is the current charge pump output of the PLL. The current can be controlled by setting the appropriate bits. The loop filter has to be designed corresponding to the chosen pump current and the internal reference frequency. A recommendation can be found in the application circuit. The charge-pump current can be chosen by setting Bit 71 and Bit 70 as follows:
Table 4-1.
Current Charge-pump Output
IPD (A) 25 100 500 2000 B71 0 0 1 1 B70 0 1 0 1
Figure 4-1.
VS
Internal Components at PDO Connection
VS
VS
PDO PD
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4.3 FMOSCIN (Pin 19)
FMOSCIN is the preamplifier input for the FM oscillator signal. Figure 4-2. Internal Components at FMOSCIN
V5
FMOSCIN
4.4
MX2LO (Pin 15)
MX2LO is the buffered output of the crystal oscillator. This signal can be used as a reference frequency for ATR4255 or ATR4258. The oscillator buffer output can be switched by the OSCB bit (B69) as follows.
Table 4-2.
MX2LO Settings
MX2LO AC Voltage ON OFF B69 0 1
Figure 4-3.
Internal Components at MX2LO
V5 V5
OSCIN MX2LO
5
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4.5
Function of DAC1, DAC2 in FM and AM Mode (Pin 3 and Pin 4)
For automatic tuner alignment, the DAC1 and DAC2 of the ATR4256 can be controlled by setting the gain of VPDO and offset values. Figure 4-4 shows the principle of the operation. In FM Mode the gain is in the range of 0.69 x V(PDO) to 2.16 x V(PDO). The offset range is +0.56V to -0.59V. For alignment, DAC1 and DAC2 are connected to the varicaps of the preselection filters. For alignment, offset and gain are set to have the best tuner tracking. Figure 4-4. Principal Operation for Alignment
Bit 34 PDO (FM) DAC1,2
Gain
+/-
Vref (AM) (3V) Offset
The DAC mode can be controlled by setting Bit 34 as follows
Table 4-3.
DAC Mode
DAC Mode FM AM B34 0 1
If Bit 34 = 1 (AM Mode), then DAC1 and DAC2 can be used as standard DAC converters. The internal voltage of 3V is connected to the gain and offset input of DAC1 and DAC2 (only in AM Mode). The gain is in the range of 0.46 x 3V to 3.03 x 3V. The offset range is +1.46V to -1.49V. Figure 4-5. Internal Components at DAC1 and DAC2 Output
VS
DAC1,2
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4.6 DAC1, DAC2 in FM Mode (Pin 3 and Pin 4)
The gains of DAC1 and DAC2 have a range of 0.69 x V(PDO) to 2.16 x V(PDO). V(PDO) is the PLL tuning voltage output. This range is divided into 256 steps; one step is approximately (2.16 - 0.46) x V(PDO) / 255 = 0.005764 x V(PDO). The gain of DAC1 can be controlled by B36 to B43 (bits 0 to 7 of DAC1 Gain), and the gain of DAC2 by B0 to B7 (bits 0 to 7 of DAC2 Gain) as follows:
Table 4-4.
DAC Gain Setting, FM Mode
B43 B7 0 0 0 0 ... 0 ... 1 1 1 B42 B6 0 0 0 0 ... 0 ... 1 1 1 B41 B5 0 0 0 0 ... 1 ... 1 1 1 B40 B4 0 0 0 0 ... 1 ... 1 1 1 B39 B3 0 0 0 0 ... 0 ... 1 1 1 B38 B2 0 0 0 0 ... 1 ... 1 1 1 B37 B1 0 0 1 1 ... 0 ... 0 1 1 B36 B0 0 1 0 1 ... 1 ... 1 0 1 Decimal Gain Decimal Gain 0 1 2 3 ... 53 ... 253 254 255
Gain DAC1, Approximately Gain DAC2, Approximately 0.69 x V(PDO) 0.69576 x V(PDO) 0.70153 x V(PDO) 0.70729 x V(PDO) ... 0.99549 x V(PDO) ... 2.14847 x V(PDO) 2.15424 x V(PDO) 2.16 x V(PDO)
Offset = 31 (intermediate position) The offset of DAC1 and DAC2 has a range of 0.56V to -0.59V. This range is divided into 64 steps; one step is approximately 1.15V / 63 = 18.25 mV. The offset of DAC1 can be controlled by B44 to B49 (bits 0 to 5 of DAC1 Offset), and the offset of DAC2 by B8 to B13 (bits 0 to 5 of DAC2 Offset) as follows:
Table 4-5.
DAC Offset Setting, FM Mode
B49 B13 0 0 0 0 ... 0 ... 1 1 1 B48 B12 0 0 0 0 ... 1 ... 1 1 1 B47 B11 0 0 0 0 ... 1 ... 1 1 1 B46 B10 0 0 0 0 ... 1 ... 1 1 1 B45 B9 0 0 1 1 ... 1 ... 0 1 1 B44 B8 0 1 0 1 ... 1 ... 1 0 1 Decimal Gain Decimal Gain 0 1 2 3 ... 31 ... 61 62 63
Offset DAC1, Approximately Offset DAC2, Approximately 0.56V 0.5417V 0.5235V 0.5052V ... +0.0059V ... 0.5535V -0.5717V -0.59V
Gain = 53 (intermediate position)
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4.7
DAC1, DAC2 in AM Mode (Pin 3 and Pin 4)
In AM mode the DAC input voltage V(PDO) is internally connected to 3V. The gains of DAC1 and DAC2 have a range of 0.46 x 3V to 3.03 x 3V. V(PDO) is the PLL tuning voltage output. This range is divided into 256 steps; one step is approximately (3.03 - 0.46) x 3V / 255 = 0.01007 x 3V. The gain of DAC1 can be controlled by B36 to B43 (bits 0 to 7 of DAC1 Gain) and the gain of DAC2 by B0 to B7 (bits 0 to 7 of DAC2 gain) as follows:
Table 4-6.
DAC Gain, AM Mode
B43 B7 0 0 0 0 ... 0 ... 1 1 1 B42 B6 0 0 0 0 ... 0 ... 1 1 1 B41 B5 0 0 0 0 ... 1 ... 1 1 1 B40 B4 0 0 0 0 ... 1 ... 1 1 1 B39 B3 0 0 0 0 ... 0 ... 1 1 1 B38 B2 0 0 0 0 ... 1 ... 1 1 1 B37 B1 0 0 1 1 ... 0 ... 0 1 1 B36 B0 0 1 0 1 ... 1 ... 1 0 1 Decimal Gain Decimal Gain 0 1 2 3 ... 53 ... 253 254 255
Gain DAC1, Approximately Gain DAC2, Approximately 0.4607 x 3V 0.4710 x 3V 0.4812 x 3V 0.4915 x 3V ... 1.0029 x 3V ... 3.0097 x 3V 3.0196 x 3V 3.0296 x 3V
Offset = 31 (intermediate position) Remark: V(PDO) is 3V in AM mode. The offset of DAC1 and DAC2 has a range of +1.46V to -1.49V. This range is divided into 64 steps; one step is approximately 2.95 V/ 63 = 46.8 mV. The offset DAC1 can be controlled by B44 to B49 (bits 0 to 5 of DAC1 Offset) and the offset of DAC2 by B8 to B13 (bits 0 to 5 of DAC2 Offset) as follows:
Table 4-7.
DAC Offset, AM Mode
B49 B13 0 0 0 0 ... 0 ... 1 1 1 B48 B12 0 0 0 0 ... 1 ... 1 1 1 B47 B11 0 0 0 0 ... 1 ... 1 1 1 B46 B10 0 0 0 0 ... 1 ... 1 1 1 B45 B9 0 0 1 1 ... 1 ... 0 1 1 B44 B8 0 1 0 1 ... 1 ... 1 0 1 Decimal Gain Decimal Gain 0 1 2 3 ... 31 ... 61 62 63
Offset DAC1 Approximately Offset DAC2 Approximately 1.4606V 1.4138V 1.3665V 1.3196V ... -0.0079V ... -1.3975V -1.4447V -1.4917V
Gain = 53 (intermediate position) 8
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4.8 DAC3 (Pin 5)
The DAC3 output voltage can be controlled by B66 to B68 (bits 0 to 2 of DAC3) as follows:
Table 4-8.
DAC3 Offset Setting
B68 0 0 0 0 1 1 1 1 B67 0 0 1 1 0 0 1 1 B66 0 1 0 1 0 1 0 1 0.55V 1.25V 1.90V 2.60V 3.30V 4.10V 4.80V 5.45V
DAC3 Offset, Approximately
Figure 4-6.
Internal Components at DAC3
VS
DAC3
4.9
EN, DATA, CLK (Pins 16 to 18)
All functions can be controlled via a 3-wire bus consisting of ENABLE, DATA and CLOCK. The bus is designed for microcontrollers which operate with 3V supply voltage. Details of the data transfer protocol are shown in "3-wire Bus Description" on page 12. Figure 4-7. Internal Components at EN, DATA, CLK
V5 EN DATA CLK
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4.10
SWO1, SWO2, SWO3 and SWO4 (Pins 7 to 10)
All switching outputs are "open drain" and can be set and reset by software control. Details are described in the data transfer protocol. The switching output SWO1 to SWO4 can be controlled as follows (B30 to B33):
Table 4-9.
SWO1 to SWO4 Setting
Switch Output SWOx = ON (switch to GND) SWOx = OFF B30 + X 0 1
X = 0 to 3 Figure 4-8. Internal Components at SWO1, SWO2, SWO3 and SWO4
SWO1 SWO2 SWO3 SWO4 I
4.11
OSCIN, OSCOUT (Pin 12 and Pin 13)
A crystal resonator (up to 15 MHz) is connected between OSCIN and OSCOUT in order to generate the reference frequency. By using the ATR4256 in connection with ATR4255 or ATR4258, the crystal frequency must be 10.25 MHz. The complete application circuit is shown in Figure 6-2. If a reference is available, it can be applied at OSCIN. The minimum voltage should be 100 mVrms. In this case, pin OSCOUT has to be open. The tuning capacity for the crystal oscillator has a range of 0.5 pF to 71.5 pF. The values are coded binary. The tuning can be controlled by B78 to B85 as follows:
Table 4-10.
B85 = 1 [pF] 0 0.5 1.0 1.5 ... 63.0 63.5
Crystal Tuning Capacitance
B85 = 0 [pF] 8.0 8.5 9.0 19.5 ... 71.0 71.5 B84 1 1 1 1 ... 0 0 B83 1 1 1 1 ... 0 0 B82 1 1 1 1 ... 0 0 B81 1 1 1 1 ... 0 0 B80 1 1 1 1 ... 0 0 B79 1 1 0 0 ... 0 0 B78 1 0 1 0 ... 0 0
10
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Figure 4-9. Internal Components at OSCIN and OSCOUT
V5
OSCIN
V5
OSCOUT
Figure 4-10. Internal Connection of Tuning Capacity for Crystal Oscillator
Cx1 Cx2
INV 8 pF 32 pF 0.5 pF 0.5 pF 32 pF 8 pF
...
...
B78 B84 B85
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5. Application Information
Figure 5-1. FMOSCIN Sensitivity
Vi (mVrms on 50)
150
100
50
0 0 20 40 60 80 100 120 140 160
Frequency (MHz)
6. 3-wire Bus Description
The register settings of ATR4256 are programmed by a 3-wire bus protocol. The bus protocol consists of separate commands. A defined number of bits are transmitted sequentially during each command. One command is used to program all the bits of one register. The different registers available (see "Data Transfer" on page 14) are addressed by the length of the command (number of transmitted bits) and by two address bits, that are unique to each register of a given length. 16-bit registers are programmed by 16-bit commands and 24-bit registers are programmed by 24-bit commands. Each bus command starts with a rising edge on the enable line (EN) and ends with a falling edge on EN. EN has to be kept HIGH during the bus command. The sequence of transmitted bits during one command starts with the LSB of the first byte and ends with the MSB of the last byte of the register addressed. To transmit one bit (0 or 1) DATA has to be set to the appropriate value (LOW or HIGH) and a LOW to HIGH transition has to be performed on the clock line (CLK) while DATA is valid. The DATA is evaluated at the rising edges of CLK. The number of LOW to HIGH transitions on CLK during the HIGH period of EN is used to determine the length of the command. The bus protocol and the register addressing of ATR4256 are compatible to the addressing used in ATR4255 and ATR4258. That means ATR4256 and ATR4255 (or ATR4258) can be operated on the same 3-wire bus as shown in the application circuit.
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Figure 6-1. 3-wire Bus Timing Diagram
tR tF VHIGH tS tR Data tHDA tS tR Clock tH tL tF VHIGH VLOW tF VHIGH VLOW tHEN VLOW
Enable
Figure 6-2.
3-wire Pulse Diagram
16-bit command
EN DATA CLK LSB BYTE 1 MSB LSB BYTE 2 MSB
24-bit command
EN DATA CLK LSB BYTE 1 MSB LSB BYTE 2 MSB LSB BYTE 3 MSB
e.g. R-Divider
2
0
21
22
23
24
25
26
27
28
29
210
211
212
213
214
215
OSCB P-2 P-2 DAC3 P-2
IPD 0 0
R-Divider
Status 0
Addr.
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6.1
Data Transfer
Control Registers
BYTE 3 STATUS 0 IPD B71 B70 DAC3 215 B65 214 213 212 210 211 29 LSB MSB BYTE 2 LSB MSB BYTE 1 LSB
Table 6-1.
A MSB ADDR. 0 0
R-Divider 28 27 B57 26 B56 25 24 23 22 21 20
OSCB 0=on, P-22 P-21 P-20 1=off B69 B68 B67 B66
B64 B63 B62 B61 B60 B59 B58
B55 B54 B53 B52 B51 B50
B MSB ADDR. 0 1 BYTE 3 STATUS 1 AM=1 SWO4 SWO3 SWO2 SWO1 0 FM=0 0=on, 0=on, 0=on, 0=on, DAC 1=off 1=off 1=off 1=off B35 B34 B33 B32 B31 B30 215 B29 214 213 212 210 211 29 LSB MSB BYTE 2 LSB MSB N-Divider 28 27 B21 26 B20 25 24 23 22 21 20 BYTE 1 LSB
B28 B27 B26 B25 B24 B23 B22
B19 B18 B17 B16 B15 B14
C MSB ADDR. 0 0 BYTE 2 DAC1 OFFSET B49 B48 B47 B46 B45 B44 B43 B42 B41 LSB MSB BYTE 1 DAC1 GAIN B40 B39 B38 B37 B36 LSB
O-25 O-24 O-23 O-22 O-21 O-20 G-27 G-26 G-27 G-25 G-24 G-23 G-22 G-20
D MSB ADDR. 0 B13 B12 BYTE 2 DAC2 OFFSET B11 B10 B9 B8 B7 B6 B5 LSB MSB BYTE 1 DAC2 GAIN B4 B3 B2 B1 B0 LSB
1 O-25 O-24 O-23 O-22 O-21 O-20 G-27 G-26 G-27 G-25 G-24 G-23 G-22 G-20
E MSB ADDR. 1 B85 B84 BYTE 2 LSB MSB 1 pF 0.5 pF B79 B78 X B77 BYTE 1 Not used X B76 X B75 X B74 X B73 X B72 LSB Oscillator tuning function B83 B82 B81 B80
0 8 pF 32 pF 16 pF 8 pF 4 pF 2 pF
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7. Absolute Maximum Ratings
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameters Analog supply voltage, pin 6 Input voltage BUS; pins 16, 17 and 18 Output current switches; pins 7, 8, 9 and 10 (see Figure 4-8 on page 10) Drain voltage switches; pins 7, 8, 9 and 10 Ambient temperature range Storage temperature range Junction temperature Electrostatic handling M.M. Symbol VS VI IO VOD Tamb Tstg Tj VESD Value 8 to 12 -0.3 to +5.3 -1 to +5 15 -40 to +85 -40 to +125 125 300 Unit V V mA V C C C V
8. Thermal Resistance
Parameters Junction ambient, when soldering to PCB Symbol RthJA Value 140 Unit K/W
9. Operating Range
All voltages are referred to GND (Pin 11) Parameters Supply voltage range, pin 6 Ambient temperature Input frequency FMOSCIN, pin 19 Programmable N, R divider Crystal reference oscillator, pins 12 and 13 Symbol VS Tamb fin SF fXTAL Min. 8 -40 15 2 0.1 Typ. 8.5 Max. 12 +85 160 65535 15 MHz Unit V C MHz
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10. Electrical Characteristics
Test Conditions (unless otherwise specified): VS = 8.5V, Tamb = 25C. No. 1 1.1 2 2.1 3 3.1 4 4.1 4.2 5 5.1 6 6.1 6.2 6.3 6.4 6.5 7 7.1 7.2 8 8.1 8.2 9 9.1 9.2 9.3 9.4 Parameters Supply Voltage Analog supply voltage Supply Current Analog supply current OSCIN Input voltage OSC Buffer (MX2LO) Output AC voltage Output DC voltage FMOSCIN Input voltage f = 15 to 120 MHz f = 120 to 160 MHz 19 FMOSC FMOSC 40 150 mVrms mVrms B B At pin15: 47 pF and 1 k 15 15 VMX2LO VMX2LO 80 1.8 120 2.0 200 2.2 mVpp V B A f = 0.1 to 15 MHz 13 OSC 100 mVrms B 6 IS 5 10 25 mA A 6 VS 8 8.5 12 V A Test Conditions Pin Symbol Min. Typ. Max. Unit Type*
Pulsed Current Output PD Output current B71 to B70 = "00" Output current B71 to B70 = "01" Output current B71 to B70 = "10" Output current B71 to B70 = "11" Leakage current PDO Saturation voltage HIGH Saturation voltage LOW SWO1, SWO2, SWO3, SWO4 (Open Drain) Output leakage current HIGH Output voltage LOW DAC1, DAC2 Output current Output voltage Maximum offset range (FM) Minimum offset range (FM) Offset = 0, Gain = 53 Offset = 63, Gain = 53 3, 4 3, 4 3, 4 3, 4 IDAC1, 2 VDAC1, 2 0.3 0.45 -0.45 0.56 -0.57 1 VS - 0.6 0.65 -0.65 mA V V V C A A A Pin 7, 8, 9, 10 over R against 8.5V I = 1 mA 7, 8, 9, 10 7, 8, 9, 10 ISWOH VSWOL 100 100 400 nA mV A A 3, 4 3, 4 8.0 0 8.5 0.4 V V A A PD = 2.5V PD = 2.5V PD = 2.5V PD = 2.5V PD = 2.5V 2 2 2 2 2 IPD IPD IPD IPD IPDL 20 80 400 1500 25 100 500 2000 30 120 600 2400 20 A A A A nA A A A A A
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
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10. Electrical Characteristics (Continued)
Test Conditions (unless otherwise specified): VS = 8.5V, Tamb = 25C. No. 9.5 9.6 10 10.1 10.2 10.3 10.4 10.5 10.6 10.7 10.8 10.9 11 11.1 11.2 11.3 Parameters Maximum gain range (FM) Minimum gain range (FM) DAC3 Output current Output voltage Output voltage Output voltage Output voltage Output voltage Output voltage Output voltage Output voltage Input voltage HIGH LOW Clock frequency Period of CLK HIGH LOW Rise time EN, DATA, CLK Fall time EN, DATA, CLK Set-up time Hold time EN Hold time DATA B68 to B66 = "000" B68 to B66 = "001" B68 to B66 = "010" B68 to B66 = "011" B68 to B66 = "100" B68 to B66 = "101" B68 to B66 = "110" B68 to B66 = "111" 5 5 5 5 5 5 5 5 5 IDAC3 VDAC3 VDAC3 VDAC3 VDAC3 VDAC3 VDAC3 VDAC3 VDAC3 0.4 1.1 1.8 2.4 3.2 3.8 4.5 5.2 0.55 1.25 1.90 2.60 3.30 4.10 4.80 5.45 1 0.7 1.4 2.1 2.8 3.5 4.3 5.0 5.7 mA V V V V V V V V C A A A A A A A A Test Conditions Gain = 255, Offset = 31 Gain = 0, Offset = 31 Pin 3, 4 3, 4 Symbol Min. 0.63 2.1 Typ. 0.69 2.16 Max. 0.75 2.23 Unit Type* A A
3-wire Bus, ENABLE, DATA, CLOCK 16 to 18 17 17 16 to 18 16 to 18 16 to 18 18 16 tH tL tr tf ts tHEN tHDA 100 250 0 250 250 400 100 VBUSH VBUSL 2.7 -0.3 5.3 +0.8 1.0 V V MHz ns ns ns ns ns ns ns A A D
11.4 11.5 11.6 11.7 11.8
D D D D D
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
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Figure 10-1. Application Circuit
EN CLK DATA C12 100 nF GND
R5 5.1k C8 47 pF 20 C1 10 pF fOSC FM VCO Vtune R4 8.2k 1 2 3 DACs 4 C16 C6 330 pF C14 C7 10 nF 10 nF C15 10 nF C4 5 6 C5 7 R2 600 LOGIC 19 18 17 BUS 16 15 14
C9 (1)
(1) (1) depends on crystal 10.25 MHz 13 12 OSC 11
Switches 8 9 10
100 nF
10 nF
100 mF R3 100
DAC1
DAC2
DAC3
VS 8V to 12V
SWO1
SWO2
SWO3
SWO4
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R407 VS (8.5V to 10.5V) C308 R29 10 100n DEV R34 27 KR202 X301 KF302 R305 1k5 C in F201 C307 C206 10n 220n C310 1n 30 29 28 27 26 25 24 23 C312 10n R152 10 C205 220n 33 32 31 10 35 34 ATR4255 1 R313 22 390 47p F131 C314 10n C110 4n7 BB804 R121 68k D131 R131 5k6 20 C104 10p 10n 1n 1 T101 BFR93A F101 BB804 R122 D101 C102 3p9 S391D 10n D103 C103 68k C159 C158 10n 10n C157 10n MPX ADJAC C115 100n C116 100n METER R151 8k2 C152 330p 2 C151 10n DAC3 SWO1 SWO3 SWO2 SWO4 3 4 5 6 7 8 9 10 C106 L102 27p 22 C56 C134 ATR4256 19 18 17 16 15 14 C156 10n 22p DATA CLK EN GND C155 100n C153 C154 12p* Q151 13 12 11 12p* 10.25 MHz *depends on Q151 C108 C109 1n C107 D102 18p BB804 R104 470 R112 47k 6p8 C133 6p8 220n C203 C114 C131 C132 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 INT IF2OUT C207 220n C208 C309 F302 10n 100p 1 C204 470n C111 44 43 42 41 40 39 38 37 36 470n R111 200k C202 C113 100n R303 1k R106 10 F201 C201 C209 100n 10n KR201 R304 1k3 MULTIP 10 C112 10 R102 68k F102
L302
C319
100 H
C306
6p8
12p
R311
2k2
Figure 10-2. Application Board Schematic
L303 2m2
R105 100
R115 1k
T102 BC858
T302 BC848
C316
R308
T301
220n
2k2
BC 858C
R306 470k
T111 J109
R307 47
C315
C302
220n
10n
C117
10n
L301
D301
47
Ant
S391D
FM 75
D302
C311
S391D
100n
R103 1k
ATR4256
19
11. Ordering Information
Extended Type Number ATR4256-TKSY ATR4256-TKQY Package SSO20 SSO20 Remarks Tube Taped and reeled
12. Package Information
Package SSO20
Dimensions in mm
6.75 6.50 5.7 5.3 4.5 4.3
1.30 0.25 0.65 5.85 20 11 0.15 0.05 0.15 6.6 6.3
technical drawings according to DIN specifications
1
10
13. Revision History
Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. Revision No. 4867D-AUDR-01/08 4867C-AUDR-10/07 4867B-AUDR-06/06 History * Section 9 "Operating Range" on page 15 changed * Put datasheet in the newest template * El. Char. table: row 5.1 changed * Put data sheet in a new template * Pb-free logo on page 1 deleted
20
ATR4256
4867D-AUDR-01/08
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4867D-AUDR-01/08

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